Computer Hardware: Logic Gates and Combinational Circuits, ISC Class 12

What Computer Hardware is about

Weightage: CISCE publishes no chapter or unit weightage for ISC Computer Science. Computer Hardware is part of Section A, 2 of the 2027 syllabus and can be asked anywhere in the 70-mark Paper 1 (Part I compulsory: ten 1-mark items and a 10-mark short-answer question; Part II: two of three 10-mark questions in each of Sections A and B, and two of three 5-mark questions in Section C).Source: CISCE ISC Computer Science (868) syllabus, examination year 2027; latest Paper 1 specimen (2025) and the 2025 board paper

Key concepts

The seven elementary gates

Gate	Expression	Output is 1 when	Truth table for A B = 00, 01, 10, 11
NOT	A'	input is 0	(one input) 0 → 1, 1 → 0
AND	A · B	all inputs are 1	0, 0, 0, 1
OR	A + B	at least one input is 1	0, 1, 1, 1
NAND	(A · B)'	not all inputs are 1	1, 1, 1, 0
NOR	(A + B)'	all inputs are 0	1, 0, 0, 0
XOR	A ⊕ B = A'B + AB'	inputs differ (odd number of 1s)	0, 1, 1, 0
XNOR	(A ⊕ B)' = AB + A'B'	inputs are equal	1, 0, 0, 1

Symbols: AND has a flat back and round front; OR has a curved back and pointed front; a small circle (bubble) at the output means NOT, which turns AND into NAND and OR into NOR; XOR has an extra curved line at the input side.

Gates in series: feed the output of one gate into the next. A gate with its inputs tied together acts as a NOT gate if it is NAND or NOR (A NAND A = A', A NOR A = A'). For example AND → NOT → NAND (inputs tied) gives back AB, i.e. the circuit behaves as an AND gate.

XOR and XNOR in words: XOR is the 'odd parity' or 'difference detector'; XNOR is the 'equality detector'.

Worked example

[2] A two-input AND gate feeds a NOT gate, whose output feeds both inputs of a NAND gate. Which single gate is the whole circuit equivalent to? Show the expressions. (Analyse)

Try it first, then show the solutionSolution

1. AND: A·B; NOT: (A·B)' - 1 mark.
2. NAND with both inputs equal to (A·B)' gives ((A·B)' · (A·B)')' = ((A·B)')' = A·B, so the circuit is an AND gate - 1 mark.

Answer: It is equivalent to an AND gate: A·B → (A·B)' → ((A·B)')' = A·B.

NAND and NOR as universal gates

A universal gate is one from which every other gate (and so every Boolean function) can be built. NAND and NOR are universal.

Using NAND only:

• NOT: A NAND A = (A·A)' = A'.
• AND: NAND followed by NAND-as-NOT: ((AB)')' = AB (2 gates).
• OR: invert each input with a NAND, then NAND them: (A'·B')' = A + B (3 gates).
• XOR: 4 NAND gates: G1 = (AB)', G2 = (A·G1)', G3 = (B·G1)', output (G2·G3)' = A ⊕ B.

Using NOR only:

• NOT: A NOR A = (A + A)' = A'.
• OR: NOR followed by NOR-as-NOT (2 gates).
• AND: invert each input with a NOR, then NOR them: (A' + B')' = AB (3 gates).
• XNOR: 4 NOR gates: G1 = (A + B)', G2 = (A + G1)', G3 = (B + G1)', output (G2 + G3)' = A XNOR B.

Converting circuits:

• An SOP (AND-OR) circuit becomes NAND-NAND: replace every gate with a NAND (because ((P)'·(Q)')' = P + Q).
• A POS (OR-AND) circuit becomes NOR-NOR: replace every gate with a NOR.

When complements of variables are available, the two-level conversion needs no extra inverters.

Worked example

[3] Build the OR function of two inputs out of nothing but NAND gates, writing the expression after each gate. (Create)

Try it first, then show the solutionSolution

1. Gate 1: A NAND A = (A·A)' = A' - 1 mark.
2. Gate 2: B NAND B = B' - 1 mark.
3. Gate 3: A' NAND B' = (A'·B')' = A + B by De Morgan - 1 mark.

Answer: Three NAND gates: two with tied inputs give A' and B', and a third NAND of A' and B' gives (A'·B')' = A + B.

Half adder and full adder

Half adder: adds two bits A and B.

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Sum = A'B + AB' = A ⊕ B; Carry = AB. Circuit: one XOR gate and one AND gate.

Full adder: adds three bits A, B and the incoming carry C.
Sum = A ⊕ B ⊕ C = Σ(1, 2, 4, 7) (1 when an odd number of inputs are 1).
Carry = AB + BC + CA = Σ(3, 5, 6, 7) (the majority function).

Direct circuit: one 3-input XOR for Sum; three AND gates and one OR gate for Carry.

From two half adders: the first half adder adds A and B (sum S1 = A ⊕ B, carry C1 = AB); the second adds S1 and C (Sum = S1 ⊕ C, carry C2 = (A ⊕ B)·C); the final Carry = C1 + C2 = AB + (A ⊕ B)C, which equals AB + BC + CA. Gates used: 2 XOR, 2 AND and 1 OR.

Application: a chain of full adders (ripple-carry adder) adds multi-bit binary numbers in the ALU.

Worked example

[2] Show that the carry of a full adder built from two half adders, AB + (A ⊕ B)C, equals AB + BC + CA. (Analyse)

Try it first, then show the solutionSolution

1. (A ⊕ B)C = AB'C + A'BC, so the carry is AB + AB'C + A'BC - 1 mark.
2. AB + AB'C = A(B + B'C) = A(B + C) = AB + AC; adding A'BC: AB + AC + A'BC = AB + AC + BC (since AB + A'BC = B(A + A'C) = B(A + C)). Truth table check: both are 1 for rows 3, 5, 6, 7 - 1 mark.

Answer: AB + (A ⊕ B)C = AB + BC + CA; both are 1 exactly for minterms 3, 5, 6, 7.

Decoders and encoders

Decoder: a combinational circuit with n input lines and up to 2^n output lines; for each input combination exactly one output is 1. It converts a binary code into a 'one-of-many' signal.
3-to-8 (binary-to-octal) decoder: inputs A, B, C (A most significant); outputs D0 = A'B'C', D1 = A'B'C, D2 = A'BC', D3 = A'BC, D4 = AB'C', D5 = AB'C, D6 = ABC', D7 = ABC. Circuit: three NOT gates and eight 3-input AND gates.
Uses: memory address decoding (selecting one memory chip or location), selecting a device, driving displays, instruction decoding, remote controls.

Encoder: the reverse of a decoder: when exactly one of its (up to) 2^n inputs is 1, the outputs give its binary code.
Octal-to-binary (8-to-3) encoder: inputs D0 to D7, outputs
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7
Circuit: three 4-input OR gates (D0 needs no connection because its code is 000).
Decimal-to-BCD (10-to-4) and hexadecimal (16-to-4) encoders follow the same idea: an output bit is the OR of all inputs whose code has 1 in that position.
Uses: keyboards (a key press is turned into a code), priority interrupt systems.

A decoder that decodes only selected codes: use one AND gate per required code, with complements where the bit is 0. For example to detect 1010 on inputs A, B, C, D use AB'CD'.

Worked example

[5] What is a decoder? Write the output expressions of a 2-to-4 decoder with inputs A and B (A most significant), name the gates needed, and state one use of an encoder. (Understand)

Try it first, then show the solutionSolution

1. Decoder: a circuit with n inputs and up to 2^n outputs in which exactly one output is 1 for each input code - 1 mark.
2. D0 = A'B' and D1 = A'B - 1 mark.
3. D2 = AB' and D3 = AB - 1 mark.
4. Gates: two NOT gates (for A' and B') and four 2-input AND gates - 1 mark.
5. Use of an encoder: a keyboard or keypad, where the single key pressed is turned into its binary code - 1 mark.

Answer: A decoder activates exactly one of its 2^n output lines for each n-bit input code. For a 2-to-4 decoder: D0 = A'B', D1 = A'B, D2 = AB', D3 = AB, built with two NOT gates and four AND gates. An encoder is used, for example, in a keyboard to convert the pressed key into a binary code.

Multiplexers

Multiplexer (MUX, data selector): a circuit with 2^n data inputs, n select lines and one output; the select lines choose which input appears at the output. It sends many inputs over one line.

2-to-1 MUX: Y = S'I0 + SI1.
4-to-1 MUX (select S1 S0): Y = S1'S0'I0 + S1'S0I1 + S1S0'I2 + S1S0I3. Circuit: two NOT gates, four 3-input AND gates and one 4-input OR gate.
8-to-1 MUX: three select lines and eight AND gates (each with 4 inputs: three select literals and one data line) feeding an 8-input OR gate.

Decoder versus multiplexer:

Decoder	Multiplexer
n inputs, up to 2^n outputs	2^n data inputs, n select lines, 1 output
Activates one of many outputs	Passes one of many inputs to the output
Converts a code to a line	Routes data (many to one)

Relation: a 3-to-8 decoder's eight AND terms are exactly the select terms of an 8-to-1 MUX. Add a data input to each AND gate and OR the eight outputs, and the decoder becomes an 8-to-1 multiplexer. (Similarly a 2-to-4 decoder leads to a 4-to-1 MUX.)

Uses of MUX: sharing a communication line among several signals, selecting data in the CPU, implementing Boolean functions.

Worked example

[2] Write the output expression of a 2-to-1 multiplexer with data inputs I0, I1 and select line S, and give its output when S = 1, I0 = 0, I1 = 1. (Apply)

Try it first, then show the solutionSolution

1. Y = S'·I0 + S·I1 - 1 mark.
2. S = 1: Y = 0·0 + 1·1 = 1 (input I1 is selected) - 1 mark.

Answer: Y = S'I0 + SI1; with S = 1, I1 is passed, so Y = 1.

Computer Hardware in real life

Each concept, met in an everyday situation. Read the situation, answer the question in your own words, then compare with the model answer. The one-line hook is what to remember.

Topics in this chapter

• Half and Full Adders, Encoders, Decoders and Multiplexers
• Logic Gates and NAND, NOR as Universal Gates

Computer Hardware: syntax and key facts

XOR and XNOR

A ⊕ B = A'B + AB'; (A ⊕ B)' = AB + A'B'

XOR: inputs differ; XNOR: inputs equal.

Half adder

Sum = A ⊕ B; Carry = AB

1 XOR + 1 AND.

Full adder

Sum = A ⊕ B ⊕ C; Carry = AB + BC + CA

From two half adders: 2 XOR, 2 AND, 1 OR.

Octal-to-binary encoder

A2 = D4+D5+D6+D7; A1 = D2+D3+D6+D7; A0 = D1+D3+D5+D7

OR gates.

4-to-1 MUX

Y = S1'S0'I0 + S1'S0I1 + S1S0'I2 + S1S0I3

AND gates + one OR gate.

Universal-gate counts (2 inputs)

NAND: NOT 1, AND 2, OR 3, XOR 4. NOR: NOT 1, OR 2, AND 3, XNOR 4

SOP → NAND-NAND; POS → NOR-NOR.

How the board asks Computer Hardware

The question patterns to expect, and the method that works for each.

Tricks to remember Computer Hardware

Short memory aids. Say each one aloud once, then use it on a question the same day.

• Encoder ORs, decoder ANDs

  EnCOder → Or gates; DecoDer → anD gates.

  Use it when: Choosing the right gate.

• Bubble = NOT

  A bubble on the output turns AND into NAND and OR into NOR.

  Use it when: Reading symbols.

• Universal counts 1-2-3-4

  NAND: NOT 1, AND 2, OR 3, XOR 4 (and the same counts for NOR with OR and AND swapped, XNOR 4).

  Use it when: Universal gate questions.

Computer Hardware: board-level solved questions

Ordered from board level to HOTS. Cover the solution, write your own, then compare step by step.

Case-study practice (Section D style)

Read the situation, then answer every part. In the board paper this is a 6-mark question split into 2 + 2 + 1 + 1 marks.

Where the marks are

How a typical answer is split into step marks. Show every step: a right final answer alone rarely earns full marks.

Where students lose marks in Computer Hardware

The slips examiners see most often, and what to write instead.

• ✗Mistake: Not understanding gates in series

  CISCE examiners' comments, 2024: on OR, NOT and NOR in series, candidates 'Answered XOR because the concept of series was not understood' and 'Used a single input for both OR and NOR gates'.

  ✓Do this: Write the expression after each gate; a NOR or NAND with tied inputs is a NOT.

  Usually costs: 1 mark.

• ✗Mistake: Wrong gates in decoders, encoders and multiplexers

  CISCE examiners' comments: in 2024 candidates 'Used OR gates instead of AND gates in the decoder circuit' and 'Drew wrong 8x1 MUX with extra select lines or interchanged MSB and LSB'; in 2025 they 'Drew a decimal or hexadecimal encoder instead of octal' and 'Used an AND gate instead of an OR gate'.

  ✓Do this: Decoder and MUX use AND gates; encoder uses OR gates. Keep A as the most significant bit; an 8-to-1 MUX has exactly three select lines.

  Usually costs: 2-3 marks.

• ✗Mistake: Skipping parts of a multi-part hardware question

  CISCE examiners' comments, 2024: candidates 'Skipped the difference between decoder and multiplexer or the last part on derived multiplexer'; in 2025 some 'Gave vague or generic applications'.

  ✓Do this: Tick off each part; give a specific application (memory address decoding, keyboard encoding).

  Usually costs: 1-2 marks.

• ✗Mistake: Using AND, OR and NOT when only NAND or NOR is allowed

  CISCE examiners' comments, 2025: candidates 'Drew circuit with AND, OR, NOT gates instead of NAND only'; in 2024 some were 'Unclear how to build OR from NAND'.

  ✓Do this: SOP → NAND-NAND; POS → NOR-NOR; show each gate's expression.

  Usually costs: 1-3 marks.

• ✗Mistake: Wrong reduction of a gate network, so the wrong gate is named

  CISCE examiners' comments, 2025: 'a single wrong output led to wrong reduction', and some 'Omitted to name/represent the gate despite correct reduction'.

  ✓Do this: Check the reduced expression against a truth table and finish with the gate's name.

  Usually costs: 1-2 marks.

Practice questions on Computer Hardware

Write each answer on paper first. Open the hint only if you are stuck, and the answer only when you have finished.

1. Q1 · 1 mark · Very short answerBoard level

   Which gate gives output 1 only when all inputs are 0?

   Hint

   Inverted OR.

   Answer

   NOR.

2. Q2 · 1 mark · Very short answerBoard level

   How many select lines does a 16-to-1 multiplexer need?

   Hint

   2^n = 16.

   Answer

   Four.

3. Q3 · 1 mark · Very short answerBoard level

   Why are NAND and NOR called universal gates?

   Hint

   Every other gate.

   Answer

   Because any Boolean function (and every other gate) can be built using only NAND gates or only NOR gates.

4. Q4 · 1 mark · Very short answerHarder board level

   Give the output of a 4-to-1 multiplexer when S1 S0 = 10 and I0 I1 I2 I3 = 0, 1, 1, 0.

   Hint

   10 selects I2.

   Answer

   1 (input I2 is selected).

5. Q5 · 2 marks · Short answerHarder board level

   [2] Construct a 2-input AND gate using NOR gates only, showing the expression at each step.

   Hint

   Invert inputs first.

   Answer

   A NOR A = A'; B NOR B = B'; A' NOR B' = (A' + B')' = AB. Three NOR gates.

6. Q6 · 3 marks · Short answerHarder board level

   [3] Show, with expressions at each gate, that four NAND gates produce XOR.

   Hint

   Common first gate.

   Answer

   G1 = (AB)'. G2 = (A·G1)' = (A(AB)')' and G3 = (B·G1)'. Output (G2·G3)' = A·G1 + B·G1 = (A + B)(A' + B') = AB' + A'B = A ⊕ B (checked by truth table).

7. Q7 · 5 marks · Long answerHOTS / competency

   [5] Draw (describe) a 4-to-1 multiplexer: truth table, expression and gates. State one use.

   Hint

   Two select lines.

   Answer

   Truth table: S1S0 = 00 → I0, 01 → I1, 10 → I2, 11 → I3. Y = S1'S0'I0 + S1'S0I1 + S1S0'I2 + S1S0I3. Gates: two NOT gates for S1', S0'; four 3-input AND gates; one 4-input OR gate. Use: sending several signals over one communication line by selecting them in turn.

8. Q8 · 5 marks · Long answerHOTS / competency

   [5] A circuit gives X = ((A + B)' + A'C)'. Simplify X, give its truth table and say for which inputs X = 1.

   Hint

   De Morgan on the outer NOR.

   Answer

   X = (A + B)·(A'C)' = (A + B)(A + C') = A + BC' (distribution). X = 1 for ABC = 010, 100, 101, 110, 111 (minterms 2, 4, 5, 6, 7), verified by truth table.

Test your recall

Answer in your head or on paper first, then open the card. Pulling an answer out of memory makes it stick far better than re-reading.

1. 1.XNOR output for equal inputs?Show answer

   1.

2. 2.Half adder carry?Show answer

   AB.

3. 3.Gates in a full adder from two half adders?Show answer

   2 XOR, 2 AND, 1 OR.

4. 4.Outputs of a 3-to-8 decoder use which gates?Show answer

   AND gates (with NOT gates for complements).

5. 5.A0 of an octal-to-binary encoder?Show answer

   D1 + D3 + D5 + D7.

Quick revision checklist

The night before the exam: can you do each of these without looking?

• ☐NAND = (AB)'; NOR = (A + B)'; XOR = A'B + AB'; XNOR = AB + A'B'.
• ☐NAND or NOR with tied inputs = NOT.
• ☐NAND: OR needs 3, XOR 4. NOR: AND needs 3, XNOR 4.
• ☐Half adder: S = A ⊕ B, C = AB. Full adder: S = A ⊕ B ⊕ C, C = AB + BC + CA.
• ☐Decoder: n → 2^n, AND gates. Encoder: 2^n → n, OR gates.
• ☐MUX: 2^n inputs, n select lines, 1 output; Y = Σ select term · Ii.
• ☐3-to-8 decoder + data inputs + OR = 8-to-1 MUX.

Computer Hardware: frequently asked questions